In some application, there is a need to use a FIFO to support communication between a processor and another processor or a functional module such as a direct memory access (DMA) controller, which is typically implemented in hardware. Typically, the FIFO management is fully implemented in hardware. The processor and/or the DMA may push data into the FIFO and pop data from the FIFO data by reading and writing at a same read address and write address. The descriptors that control the accessing of data within the FIFO are maintained in registers that are embedded within the FIFO control logic. The control logic updates the descriptors in response to read and write accesses to the read and write address of the FIFO by the processor and/or DMA. The control logic determines when the FIFO is empty or full and provides status indicators of the current state of the FIFO.
In some applications, several FIFOs may be needed. In order to reduce the amount of hardware required for the FIFO controllers, the descriptors of the FIFO may be located in a portion of the processors memory to save area. In this arrangement, the processor needs to access the memory to update the pointers when it makes an access to the FIFO. The sequence of generic processor instructions is quite long, as follows:
Extract the size, the base address, R/W pointers, etc fields from the FIFO descriptor;
Compute the read or the write pointer in the SRAM;
Check if the FIFO is full for a write operation or empty for a read operation
Compute the new read and write pointer with a circular addressing scheme;
Compute the number of elements in the FIFO to process according to a threshold; and
Save the result in memory.
However, executing this complex sequence of generic processor instructions each time a piece of data is written to or read from the FIFO requires a large number of execution cycles by the processor which may impinge on other tasks being performed by the processor.